`timescale 1 ns / 100 ps 		//modify the parameters accordingly

module ClockDivider_tb;

	reg CLK_50MHz;
	reg rst_n;
	wire CLK_100Hz;
	wire CLK_1Hz;

	ClockDivider dut (
		CLK_50MHz,
		rst_n,
		CLK_100Hz,
		CLK_1Hz
	);


	initial CLK_50MHz = 0;
	always #10 CLK_50MHz = ~CLK_50MHz;

	initial begin
		rst_n = 0;
		#100;
		rst_n = 1;
		#1000000;
		$finish;
	end
	

	reg last_clk1 = 0;
	always @(posedge CLK_1Hz or negedge CLK_1Hz) begin
		if (CLK_1Hz !== last_clk1) begin
			$display("Time = %0t ns | CLK_1Hz toggled to %b", $realtime / 1000.0, CLK_1Hz);
		end
		last_clk1 <= CLK_1Hz;
	end
/*

	reg last_clk100 = 0;
	always @(posedge CLK_100Hz or negedge CLK_100Hz) begin
		if (CLK_100Hz !== last_clk100) begin
			$display("Time = %.0f ns | CLK_100Hz toggled to %b", $realtime , CLK_100Hz);
		end
		last_clk100 <= CLK_100Hz;
	end
*/
endmodule
